Is the MIPS CPU cycle-accurate?
Is the MIPS CPU cycle-accurate?
I'm wondering if the current CEN64 version implements the 100% of the instruction set of the N64 MIPS CPU (including 64bit addressing ABI) and if it's cycle accurate or a hack.
I'm asking this because I was an SGI developer quite a few years ago, and I remember it wasn't easy to predict exact execution times because the MIPS CPUs were relatively complex (well, maybe I'm thinking in the R10K which had predictive branching and related stuff... The R4K family was simpler, but also had caches, which I guess would complicate a cycle-accurate emulation).
I'm asking this because I was an SGI developer quite a few years ago, and I remember it wasn't easy to predict exact execution times because the MIPS CPUs were relatively complex (well, maybe I'm thinking in the R10K which had predictive branching and related stuff... The R4K family was simpler, but also had caches, which I guess would complicate a cycle-accurate emulation).
- MarathonMan
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Re: Is the MIPS CPU cycle-accurate?
Not 100% cycle-accurate - I'm still missing some of the slips and stalls.
But largely, yes. The model is quite solid and things like multi-cycle operations, use-after-load stalls, etc. are all implemented. The memory system is fixed-delay right now (until I figure out a better way to simulate the RDRAM and bus activity), so CACHE and memory-operations do stall as they should, but only for a constant delay, which isn't entirely correct.
The R4k (and in particular, the R4200/R4300i - the runts of the family) are particularly easy to simulate compared to the pipelines that you speak of. The pipelines are a simple 5 stage design straight out of Hennessy and Patterson - fetch/decode/execute/memory/writeback. There's no branch prediction to worry about and the caches are quite small (and direct-mapped - not even set-associative), so you can count on most commercial ROMs generating quite a few stalls.
EDIT: Thanks, this post got me thinking about a slip that I haven't implemented yet, but would be quite easy to add in and will help improve performance with most commercial carts.
EDIT 2: Didn't result in a speed-up, but at least things are more accurate now. DCM, DCB, LDI, MCI, ICB, and a few more are all implemented. Really, the only thing that's left is micro-TLB stalls (ITM), and CP0I -- others like BRPT, IBE, DBE, etc. are not implemented either, but aren't timing-related, just raised on events that don't happen in an ordinary ROM.
But largely, yes. The model is quite solid and things like multi-cycle operations, use-after-load stalls, etc. are all implemented. The memory system is fixed-delay right now (until I figure out a better way to simulate the RDRAM and bus activity), so CACHE and memory-operations do stall as they should, but only for a constant delay, which isn't entirely correct.
The R4k (and in particular, the R4200/R4300i - the runts of the family) are particularly easy to simulate compared to the pipelines that you speak of. The pipelines are a simple 5 stage design straight out of Hennessy and Patterson - fetch/decode/execute/memory/writeback. There's no branch prediction to worry about and the caches are quite small (and direct-mapped - not even set-associative), so you can count on most commercial ROMs generating quite a few stalls.
EDIT: Thanks, this post got me thinking about a slip that I haven't implemented yet, but would be quite easy to add in and will help improve performance with most commercial carts.

EDIT 2: Didn't result in a speed-up, but at least things are more accurate now. DCM, DCB, LDI, MCI, ICB, and a few more are all implemented. Really, the only thing that's left is micro-TLB stalls (ITM), and CP0I -- others like BRPT, IBE, DBE, etc. are not implemented either, but aren't timing-related, just raised on events that don't happen in an ordinary ROM.
Re: Is the MIPS CPU cycle-accurate?
I'm happy my curiosity was of help 

- Breadwinka
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Re: Is the MIPS CPU cycle-accurate?
Will the build bot put up new builds on the site any time soon?
- MarathonMan
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Re: Is the MIPS CPU cycle-accurate?
The build bot isn't building the Windows binaries correctly (they compile and functionally execute OK, but there's a performance regression).Breadwinka wrote:Will the build bot put up new builds on the site any time soon?
For now, I've been doing it manually, which means less-frequent update cycles until I track down the issue.
I'll try to push a build relatively soon, though.
- MarathonMan
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Re: Is the MIPS CPU cycle-accurate?
Bump. Pushed new builds.Breadwinka wrote:Will the build bot put up new builds on the site any time soon?
- Breadwinka
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Re: Is the MIPS CPU cycle-accurate?
awesome, also looks like google is flagging your http://downloads.cen64.com/ as malware.MarathonMan wrote:Bump. Pushed new builds.Breadwinka wrote:Will the build bot put up new builds on the site any time soon?
- MarathonMan
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Re: Is the MIPS CPU cycle-accurate?
Yeah, I already filed a report about that.Breadwinka wrote:awesome, also looks like google is flagging your http://downloads.cen64.com/ as malware.
Re: Is the MIPS CPU cycle-accurate?
I had the same problem with firefox on some other legitimate site. People are going around flagging legit sites for malware. It's annoying.
- MarathonMan
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Re: Is the MIPS CPU cycle-accurate?
Should be cleared up now on all browsers.
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